Triangle clipper unit design for graphics processing unit | |
| Author | Gajasinghe, Rajapaksha Waththegedara Randil Lalinda |
| Call Number | AIT Thesis no.ISE-12-39 |
| Subject(s) | Graphics processing units Polygons |
| Note | A thesis submitted in partial fulfillment of the requirements for the degree of Master of Engineering in Microelectronics and Embedded Systems, School of Engineering and Technology |
| Publisher | Asian Institute of Technology |
| Series Statement | Thesis ; no. ISE-12-39 |
| Abstract | Polygon Clipping is the task of discarding primitives and parts of primitives that fall outside the visible volume in a real time rendering pipeline. By discarding invisible parts of the 3D virtual world, the workload for the complex circuitry that appears down the pipeline is reduced vastly. This thesis proposes optimized algorithms and hardware designs for polygon clipping in the real time rendering pipeline. The outcode method is used for trivial rejection of primitives that are completely outside the visible volume. Two algorithms are proposed for clipping primitives that intersect the boundaries of the visible volume. One algorithm favours pipelined implementation consuming more area and more power. This algorithm offers faster operation. The second algorithm favours non-pipelined implementation. This algorithm is slower than the first algorithm, but consumes less area and less power. Two hardware designs are proposed based on the two algorithms. One design can process up to 30 million triangles per second at 84 MHz clock speed with a power consumption of 111.74 mW. The other design can process up to 20 million triangles per second at 81 MHz clock speed while consuming approximately one fourth the area of the first design. The power consumption of this design is 78.88 mW. These performance parameters were estimated for implementation in a Virtex 6 FPGA, the performance would further improve for ASIC implementation. |
| Year | 2012 |
| Corresponding Series Added Entry | Asian Institute of Technology. Thesis ; no. ISE-12-39 |
| Type | Thesis |
| School | School of Engineering and Technology (SET) |
| Department | Department of Industrial Systems Engineering (DISE) |
| Academic Program/FoS | Industrial Systems Engineering (ISE) |
| Chairperson(s) | Mongkol Ekpanyapong |
| Examination Committee(s) | Bohez, Erik L.J.;Guha, Sumanta;Chumnarn Punyasai |
| Scholarship Donor(s) | Thailand (HM King) |
| Degree | Thesis (M. Eng.) - Asian Institute of Technology, 2012 |