| Abstract | In the general transmission system, the information data transmitting from the sender to the receiver may get corrupted due to the noise signal in the channel. There are many techniques that help controlling the error in the data. Each technique has its own advantages and disadvantages and may only be suitable for some applications. In this research, the Forward error correction (FEC) technique is chosen in correcting the error in the information data in the Third-generation (3G) mobile systems. Its technique involves applying the error correcting codes (ECCs) to the information data in order to calculate the redundancy data that the receiver is able to use to recover the original information data. The Low-density parity-check (LDPC) codes are chosen as the ECCs for the mobile application since the LDPC codes, as of present, have the potential to yield the better decoding performance and throughput than any other codes. The research in designing a good error correcting decoder that can be compatible with the Third-generation (3G) mobile standards has been focused in which it needs to comply with the 3G standard by meeting the throughput, bit error rate, and latency requirements of the 3G. In addition, the implementation of the decoder on hardware is necessary for the mobile application. However, the LDPC decoder generally requires a high number of components in its design in order to yield the acceptable decoding performance. Thus, implementing The LDPC decoder results in a very high utilization in hardware area and becomes a difficult task for hardware implementation such as in the field programmable gate array (FPGA) due to its limited hardware area. In order to overcome the obstacle of the hardware implementation, in this research, it proposes a novel approach in combining the Cycle-invariant different sets (CIDS), and the Decoder-first design techniques for the LDPC decoder implementation. These combinations of techniques enable the design of the LDPC decoder to function on the Virtex-5 FPGA while meeting the throughput, bit error rate, and latency requirements of the 3G. In addition, the implementation of the decoder on hardware is necessary for the mobile application. However, the LDPC decoder generally requires a high number of components in its design in order to yield the acceptable decoding performance. Thus, implementing The LDPC decoder results in a very high utilization in hardware area and becomes a difficult task for hardware implementation such as in the field programmable gate array (FPGA) due to its limited hardware area. In order to overcome the obstacle of the hardware implementation, in this research, it proposes a novel approach in combining the Cycle-invariant different sets (CIDS), and the Decoder-first design techniques for the LDPC decoder implementation. These combinations of techniques enable the design of the LDPC decoder to function on the Virtex-5 FPGA while meeting the throughput, bit error rate, and latency requirements of 3G in order to comply with the 3G standard. |