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FPGA based video compression using BDD | |
Author | Mongkol Ekpanyapong |
Call Number | AIT Thesis no. CS-00-05 |
Subject(s) | Video compression |
Note | A thesis submitted in partial fulfillment of the requirements for the degree of Master of Engineering, School of Advanced Technologies |
Publisher | Asian Institute of Technology |
Series Statement | Thesis ; no. CS-00-05 |
Abstract | Recent development on a new paradigm involving image mapping by using Ordered Binary Decision Diagram (OBDD) has significantly shown the effectiveness in both the image compression and recognition. Nevertheless, there are many applications related to image processing that have not yet been explored. Video compression is one such application that could benefit from the use of OBDD as the boolean operation required by the video compression can be directly applied to OBDD. In this research, video compression using OBDD representation is designed and implemented. As an alternative to the software based, reconfigurable computing is employed to enable higher degree of computing speed. Using this approach, simulation experiment shows that video compression speed using reconfigurable computing gains thousands times faster than the one based on software alone. The compression ratio ranges from 3:1-10:1 depends on the patterns of video input. |
Year | 2000 |
Corresponding Series Added Entry | Asian Institute of Technology. Thesis ; no. CS-00-05 |
Type | Thesis |
School | School of Advanced Technologies (SAT) |
Department | Department of Information and Communications Technologies (DICT) |
Academic Program/FoS | Computer Science (CS) |
Chairperson(s) | Kanchana Kanchanasut; |
Examination Committee(s) | Chidchanok Lursinsap;Aekavute Sujarae; |
Scholarship Donor(s) | Asian Institute of Technology; |
Degree | Thesis (M.Eng.) - Asian Institute of Technology, 2000 |