Design of DDR-SDRAM controller in a re-configurable Computing system for digital image processing | |
| Author | Mr. Damrongsak Tongsompom |
| Call Number | AIT Thesis no.ME-02-07 |
| Subject(s) | Configurations Computer storage devices Random access memory |
| Note | A thesis submitted in partial fulfillment of the requirements for the degree of Master of Engineering, School of Advanced Technologies |
| Publisher | Asian Institute of Technology |
| Series Statement | Thesis ; no. ME-02-07 |
| Abstract | A design of high speed data storage system is introduced in this thesis to implement a re-configurable computing system for digital image processing. Frames of picture which are changed to be a bit stream must be stored in the memory. In the digital image processing system, it may need many frames of picture to process. Then, the memory should have high capacity. It results in the dynamic RAM such DDR SDRAM selected to use in this application. Because a processor core in a re-configurable computing system requires high bandwidth communication for the triple task interfaces, a communication between the processor core and memory must be in a high data rate. In this design, a high speed DDR SDRAM controller and a digital image processing interface are the main consideration. However, the printed circuit board (PCB) is also considered for a board level implementation. The workload on the high speed DDR SDRAM controller design consists of the memory controller design and clock distribution management. Clock distribution management is considered to generate and supply clock to all parts of DDR SDRAM controller in FPGA and DDR SDRAM with de-skew and approach zero delay. The memory controller is designed to meet the required data rate of the communication. The workload on the digital image processing interface is between the digital image processing system and the data in the memory. It features the digital image processing algorithm which can select to access to each pixel in any frames of picture. Both the DDR SDRAM controller and digital image processing interface are designed by using Hardware Description Language (HDL). Finally, these DDR SDRAM controller and digital image processing interface are implemented as a part of a reconfigurable computing system in FPGA. For the board level implementation, the PCB is considered about the delay time for a chip-to-chip communication. This delay time is occurred by the metal line parasitic. Line capacitance is modeled by using parallel-plate capacitor model while line resistance is modeled based on a sheet resistance. |
| Year | 2002 |
| Corresponding Series Added Entry | Asian Institute of Technology. Thesis ; no. ME-02-07 |
| Type | Thesis |
| School | School of Advanced Technologies (SAT) |
| Department | Department of Industrial Systems Engineering (DISE) |
| Academic Program/FoS | Microelectronics (ME) |
| Chairperson(s) | Lertsak Lekawat;Afzulpurkar, Nitin V.; |
| Examination Committee(s) | Oesch, Helmut;Chumnam Punyasai;Waidelich, Markus; |
| Scholarship Donor(s) | Asian Institute of Technology - Partial Scholarship;Royal Thai Government Fellowship; |
| Degree | Thesis (M.Eng.) - Asian Institute of Technology, 2002 |