| Author | Ranawaka, R.A.D.M.P |
| Note | A thesis submitted in partial fulfillment of the requirements for the degree of Master of
Engineering in Micro-Electronics and Embedded Systems |
| Publisher | Asian Institute of Technology |
| Abstract | Real time stream processing mainly video processing plays a key role in many modern day application segments such as Computer Vision, Surveillance, Machine Vision and Robotics. Conventional sequential processing on software with a general purpose CPU has become significantly insufficient due to the high demand of processing power to deliver adequate throughput and performance. Due to the cost of centralized processing and cost of heavy data transmission, portability, mobility, power consumption and many such reasons a high degree of interest could be noted for high performance real time video processing on localized embedded systems. However, embedded processing platforms with limited performance could not cater the processing demand of several such intensive applications in computer vision domain. Therefore, hardware acceleration could be noted as an ideal solution where process intensive computations or algorithms could be accelerated using application specific hardware designed in stream processing fashion. In this research we focus on building such a hardware accelerator/ video co-processing unit for Histogram of Gradients(HOG) algorithm which is one such versatile computer vision algorithm in contrast to high demand for processing power. This research explores the possibility of using high performance computing techniques used in general purpose processors such as pipelining and parallel processing for developing a high performance stream processing architecture on the accelerator.Robust architectural techniques were developed to maximize hardware and computation reuse and minimize hardware utilization and redundant computations. Additionally robust buffering techniques were developed to custom suit the processing logic while maintaining streaming flow of data which ensures only minimum necessary data is buffered and processed in parallel while meeting the throughput requirement at each stage. This stream processing architecture yielded a promising throughput 240fps on single scale HOG computation with very low amount of hardware which outperforms all previous research. In comparing with the best case performance of the previous research its a performance gain of approximately four times with equal or lesser hardware. Further the above video processing unit(VPU) acts as a hardware accelerator which is integrated as co-processing peripheral to a host CPU with a on chip bus in a System-OnChip (SoC) fashion. This could be used to offload the heavy video stream processing and redundant computations to the VPU whereas the processing power of the CPU could be preserved for running light weight applications. Functionality of the video SoC could be further extended by implementing an operating system on the CPU which encapsulates the behavior of the accelerator as a hardware thread to the high level application programmer. In addition a robust and compact System-on-Chip (SoC) could deliver higher performance per watt, higher performance per hardware utilization/silicon area, compactness and reliability. This kind of a hardware acceleration approach is highly recommended for an application with fixed functionality in contrast to a traditional and heavy general purpose computing architecture which demands an exponentially larger amount of hardware and power to meet an identical throughput requirement. |
| Year | 2017 |
| Type | Thesis |
| School | School of Engineering and Technology (SET) |
| Department | Department of Industrial Systems Engineering (DISE) |
| Academic Program/FoS | Microelectronics (ME) |
| Chairperson(s) | Mongkol Ekpanyapong; |
| Examination Committee(s) | Tavares, Adriano;Daily, Matthew N.;Krit Athkulwongse |
| Scholarship Donor(s) | AIT Fellowship |
| Degree | Thesis (M.Eng.) -- Asian Institute of Technology, 2017 |