| Author | Thilakasiri, Laddusinghe Badu Hasini Thilanka |
| Note | A thesis submitted in partial fulfillment of the requirements for the
degree of Master of Engineering in
Microelectronics and Embedded Systems |
| Publisher | Asian Institute of Technology |
| Abstract | Recent research on neural networks have shown a significant advancement in computer vision over traditional algorithms based on handcrafted features and models. Deep Convolutional Neural Network (CNN) dependant models are the best sophisticated mechanism for the tasks of object classification and object detection. Although their advancement over traditional methods is significant, their huge networks and models are very computationally costly. Compared to object classifiers, this is even worse when it comes to CNN based real time object detectors. They process on powerful GPUs that uses lots of power. CPU platforms are hard to provide sufficient computation resources to run these large networks. Due to the higher computational capabilities and ease of use in development frameworks GPUs are first selection in neural network processes. Although GPUs are highly capable of processing high computational costly models, they are power hungry and low in energy efficiency. In the meantime, Field Programmable Gate Array (FPGA) based neural network accelerator is becoming a research topic. With specifically designed hardware, FPGA is the next possible solution to surpass GPU in speed and energy efficiency. With the current need of optimized, energy efficient CNN models; we can use FPGAs to research on new optimized, energy efficient and simpler models of existing state-of-art CNN networks, that we can run on low power embedded processors as well. In this research we are going to optimize You Only Look Once (YOLO) real time object detection architecture on FPGA, to reduce its computational cost and increase the power efficiency, while keeping up the accuracy of the network at a reasonable level. |
| Year | 2019 |
| Type | Thesis |
| School | School of Engineering and Technology (SET) |
| Department | Department of Industrial Systems Engineering (DISE) |
| Academic Program/FoS | Microelectronics (ME) |
| Chairperson(s) | Mongkol Ekpanyapong; |
| Examination Committee(s) | Dailey, Matthew;Abeykoon, A.M. Harsha S. ; |
| Scholarship Donor(s) | His Majesty the King’s Scholarships (Thailand); |
| Degree | Thesis (M.Eng.) -- Asian Insitute of Technology, 2019 |