Clock and data recovery for SONET OC-12 system | |
| Author | Tom Takan |
| Call Number | AIT Thesis no.ME-05-06 |
| Subject(s) | SONET (Data transmission) Data recovery (Computer science) Data transmission systems Metal oxide semiconductors, Complementary |
| Note | A thesis submitted in partial fulfillment of the requirements for the degree of Master of Engineering, School of Advanced Technologies |
| Publisher | Asian Institute of Technology |
| Series Statement | Thesis ; no. ME-05-06 |
| Abstract | This thesis describes the architecture and components of a high-speed clock and data recovery (CDR) circuit. The CMOS circuits are presented for an integrated physical layer controller of a 622-Mb/s (OC-12) system. Simulations and experimental results are presented for the building blocks including novel designs for a current-controlled oscillator (CCO) and a charge pump. The CCO is based on a two-stage ring oscillator. It consists of parallel differential amplifier pairs which reliably generate the necessary phase shift and gain to fulfill the oscillation conditions over process and temperature variations. The schematics are implemented in C11 (0.13 µm CMOS). One contains partitioned building blocks of a phase-locked loop (PLL) which, together with an external capacitor loop filter. |
| Year | 2005 |
| Corresponding Series Added Entry | Asian Institute of Technology. Thesis ; no. ME-05-06 |
| Type | Thesis |
| School | School of Advanced Technologies (SAT) |
| Department | Department of Industrial Systems Engineering (DISE) |
| Academic Program/FoS | Microelectronics (ME) |
| Chairperson(s) | Lertsak Lekawat; |
| Examination Committee(s) | Afzulpurkar, Nitin V. ;Dutta, Joydeep ;Chumnarn Punyasai; |
| Scholarship Donor(s) | Asian Institute of Technology Fellowship; |
| Degree | Thesis (M.Eng.) - Asian Institute of Technology, 2005 |