EPGA implementation of rank order median filter for mobile robots | |
| Author | Arumugam, Geethamani |
| Call Number | AIT Thesis no.ISE-06-17 |
| Subject(s) | Mobile robots Computer algorithms |
| Note | A thesis submitted in partial fulfillment of the requirements for the degree of Master of Engineering, School of Engineering and Technology |
| Publisher | Asian Institute of Technology |
| Series Statement | Thesis ; no. ISE-06-17 |
| Abstract | Computer manipulation of images is generally defined as Digital image processing (DIP). DIP is used in variety of applications, including video surveillance, target recognition, and image enhancement. Some of the many algorithms used in image processing include rank order filter, edge detection and contrast enhancement. The goal of this thesis is to implement image processing by Median filter algorithm for mobile robot on FPGA using VHDL implementation on a general-purpose Altera's FPGA board. Image processing is a very important field within industrial automation, and more concretely, in the automated visual inspection. These are usually implemented in software but may use special purpose hardware for speed. With advances in the VLSI technology, hardware implementation of DIP has become an attractive alternative. In this thesis the image processing algorithms like median filter, basic morphological operators are implemented on FPGA. Median filter, a part of rank-order filter is a robust method to remove the impulsive noise from an image. It is a computationally intensive operation, so it is hard to implement it in real time. This thesis introduces a new architecture and optimizations for its implementation with FPGAs. The software results show the effectiveness of the improvements allowing real-time processing and a minimum use of resources. Due to time constraint the software design of the median filter algorithm is implemented on Altera's Cyclone II EP2C35F672C7 device using Altera's EDA tool Quartus® II version 4.1. This algorithm is very efficient and the results show the significant improvements in operating frequency and hardware requirements over general-purpose techniques |
| Year | 2006 |
| Corresponding Series Added Entry | Asian Institute of Technology. Thesis ; no. ISE-06-17 |
| Type | Thesis |
| School | School of Engineering and Technology (SET) |
| Department | Department of Industrial Systems Engineering (DISE) |
| Academic Program/FoS | Industrial Systems Engineering (ISE) |
| Chairperson(s) | Afzulpurkar, Nitin V.; |
| Examination Committee(s) | Manukid Parnikhun;Guha Sumanta; |
| Scholarship Donor(s) | Asian Institute of Technology Fellowship; |
| Degree | Thesis (M.Eng.) - Asian Institute of Technology, 2006 |