| Author | Nataraj, Manjunath |
| Call Number | AIT Thesis no.ME-06-05 |
| Subject(s) | PCI bus (Computer bus)
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| Note | A thesis submitted in partial fulfillment of the requirements for the degree of Master of Engineering, School of Engineering and Technology |
| Publisher | Asian Institute of Technology |
| Series Statement | Thesis ; no. ME-06-05 |
| Abstract | The PCI (Peripheral Component Interface) Local Bus is a high performance 32bit or 64 bit bus with multiplexed address and data lines. The bus is intended to be used as an interconnect mechanism between highly integrated peripheral controller components, peripheral add-in boards, an processor/memory systems. The current PCI Local Bus revision 2.2 operates at 66 MHz. The focus of the problem is to enhance the performance of this system by increasing the speed to 100 MHz. This thesis work is focused on the physical design of enhanced PCI Local Bus revision 2.2. Physical design is the process of translating structural representation into layout representation, the layout must satisfy geometric, timing and power-consumption constraints. The physical design flow which consists of design import, floorplanning and power planning, placement, routing, timing analysis and timing optimizations steps are carried out. The main challenge of this thesis work is to meet the tough timing constraints set by the logic designer. The floorplanning affect the timing performance significantly and forms the most important step of this thesis work. The PCI system has three clocks operating at 162 MHz, 121 MHz and 100MHz. In meeting these tough timing constraints floorplanning plays a major role. Here a novel floorplanning technique is used, which is manual floorplanning. The results from both the automated floorplanned design and manually floorplanned design is compared analyzed |
| Year | 2006 |
| Corresponding Series Added Entry | Asian Institute of Technology. Thesis ; no. ME-06-05 |
| Type | Thesis |
| School | School of Engineering and Technology (SET) |
| Department | Department of Industrial Systems Engineering (DISE) |
| Academic Program/FoS | Microelectronics (ME) |
| Chairperson(s) | Afzulpurkar, Nitin V.;Lertsak Lekawat; |
| Examination Committee(s) | Chumnarn Punyasai; |
| Scholarship Donor(s) | Asian Institute of Technology Fellowship; |
| Degree | Thesis (M.Eng.) - Asian Institute of Technology, 2006 |