| Author | Hasan, Md. Arif |
| Call Number | AIT Thesis no.ME-07-05 |
| Subject(s) | Frequency synthesizers
|
| Note | A thesis submitted in partial fulfillment of the requirements for the
degree of Master of Science in Microelectronics, School of Engineering and Technology |
| Publisher | Asian Institute of Technology |
| Series Statement | Thesis ; no. ME-07-05 |
| Abstract | Wireless communication has undergone an unbelievable development over the past few years. The rapid development of wireless communication has lead to an increasing demand of low-cost, low-power and high-performance Integrated Circuits (ICs). Short Communication Network, Bluetooth or Wireless Local Area Network (WLAN), Zigbee has replaced the old cable communication. New low-power, low-rate standards, such as Bluetooth or Zigbee, imposes new area and power reduction constraints due to its main fields of application. Area, cost and power constraints may be solved by means of integrating the digital and RF sections of these transceivers with the same well-known CMOS technology. In order to meet the growing demand for these short wireless communication networks, it is desirable to implement some transceivers monolithically with the help of improving large-scale low-cost integration technology. Frequency synthesizers are an integral part of any transceiver systems for the generation of the local oscillator (LO) that is used for the up/down conversion of radio frequency (RF) signals from/to intermediate frequency (IF) or base-band signals. Even though frequency synthesizer theory is very mature, there is still a large research effort aimed to improve performance and optimize implementations for new technologies and emerging standards. One of the main drivers for research and technical advancements in frequency synthesizers is for the need to generate increasingly higher frequencies while decreasing power consumption. From the cost and area perspective, latest lowest transistor size based ASIC tool, reduced supply voltage, reduced component count on the chip design is important. The thesis was carried out with UMC O.18 um technology with 1 volt supply voltage. To reduce the power consumption more, the most power hungry block, prescaler was designed with TSPC based design with DTMOS technique. DTMOS technique was also applied in the amplifier design. Ring oscillator was designed instead of conventional LC tank to reduce the area of the chip and thus to serve the cost effectiveness. The overall power consumption was measured around 29m W |
| Year | 2007 |
| Corresponding Series Added Entry | Asian Institute of Technology. Thesis ; no. ME-07-05 |
| Type | Thesis |
| School | School of Engineering and Technology (SET) |
| Department | Department of Industrial Systems Engineering (DISE) |
| Academic Program/FoS | Microelectronics (ME) |
| Chairperson(s) | Lertsak Lekawat; |
| Examination Committee(s) | Apinunt Thanachayanont;Chumnarn Punyasai; |
| Scholarship Donor(s) | Asian Institute of Technology Fellowship; |
| Degree | Thesis (M.Sc.) - Asian Institute of Technology, 2007 |