Implementation of pixel architecture with correlated double sampling in CMOS image sensor | |
| Author | Vyas, Agin |
| Call Number | AIT Caps. Proj. no.EL-14-02 |
| Subject(s) | Metal oxide semiconductors, Complementary Image processing Digital techniques |
| Note | A capstone project submitted in partial fulfillment of the requirements for the degree of Bachelor of Area Name in Electronics Engineering, School of Engineering and Technology |
| Publisher | Asian Institute of Technology |
| Series Statement | Caps. Proj. ; no. EL-14-02 |
| Abstract | Ever increasing demands of miniaturisation on smart CMOS camera sensors require innovative and efficient arechitecture and space conserving layouts that render themselves to robust manufacturing.. In 0.8m cleanroom technology, pixel layout creation needs high precision and accuracy in details. This project describes an attempt to design a 5050 pixel with three transistors and a photodiode in conjuction with a 5046 correlated double sampling circuit, incorporated into a 64x64 array. Layouts have been prepared using known VLSI design techniques in Cadence software which are organized, effective and area conserving with 82.6% pixel fill factor and a semi-edge detecting sampling circuit. |
| Year | 2014 |
| Corresponding Series Added Entry | Asian Institute of Technology. Caps. Proj. ; no. EL-14-02 |
| Type | Project |
| School | School of Engineering and Technology |
| Department | Bachelor Degree |
| Academic Program/FoS | Electronic Engineering (EL) |
| Chairperson(s) | Mongkol Ekpanyapong; |
| Examination Committee(s) | Chumnarn Punyasai; |
| Degree | Capstone Project (B.Sc.)-Asian Institute of Technology, 2014 |