Design of an Improved Low Noise CMOS Differential Amplifier for a Digital Image Sensor Application | |
| Author | Bandara, Menama Rallage Kasun Janitha |
| Call Number | AIT Caps. Proj. no.EL-14-07 |
| Subject(s) | Image processing Digital techniques Metal oxide semiconductors, Complementary |
| Note | A capstone project submitted in partial fulfillment of the requirements for the degree of bachelor of science in Electronics Engineering, School of Engineering and Technology |
| Publisher | Asian Institute of Technology |
| Series Statement | Caps. Proj. ; no. EL-14-07 |
| Abstract | With the rapid advancement of the analog electronics technology, different types of sensing devices were developed by several companies in the world, Most of the times the natural environment behaves in analog form. This project is also related to the analog electronics and it is about a CMOS image sensor. This article focuses only on the analog signal amplifier par. The main aim is to design a low noise differential amplifier to the given parameters and design the respective fabricating layout. As for the requirements the overall gain of the amplifier should be 60+ dB and the UGB should be 10 MHz for the given feedback configuration. It also expects a minimum offset voltage with a maximum SNR, CMRR and PSRR including some other facts. The design process was first done using manual calculations and later with CADENCE software. The proposed circuit is a 3 stage amplifier with the first stage as the differential stage and second and third stages as common source Cascode amplifiers. The differential stage was designed using PMOS differential pair while the other stages are designed totally with NMOS. A miller capacitor is used at the final stage to achieve the desired UGB. The simulations were done using analog environment analysis and the AC,DC Noise and Transient responses are analyzed for both open loop and closed loop configurations. Outputs plots were analyzed and layout was drawn using LayoutXL. All the verifications such as DRC and LVS were passed Layout optimization was done along with the post layout simulation. Final results were obtained using simulation which showed almost ner values with the manual estimations. The simulated gain was about 64.54 dB and the UGB was about 9.6MHZ. |
| Year | 2014 |
| Corresponding Series Added Entry | Asian Institute of Technology. Caps. Proj. ; no. EL-14-07 |
| Type | Project |
| School | School of Engineering and Technology |
| Department | Bachelor Degree |
| Academic Program/FoS | Electronic Engineering (EL) |
| Chairperson(s) | Mongkol Ekpanyapong; |
| Examination Committee(s) | Chumnarn Punyasai; |
| Degree | Capstone Project (B.Sc.)-Asian Institute of Technology, 2014 |