Designing rate monotonic scheduling in processor core with multi-threading for ARM architecture | |
| Author | Tamrakar, Sujan |
| Call Number | AIT Caps. Proj. no.EL-15-05 |
| Subject(s) | System design Data processing Computer architecture |
| Note | A capstone project report submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Engineering Electronics Engineering, School of Engineeringa and Technology |
| Publisher | Asian Institute of Technology |
| Series Statement | Caps. Proj. ; no. EL-15-05 |
| Abstract | In order to better utilize the resources of processor core and increase the performance efficiency of the core multithreading in a single processor can be implemented. In the main three parts of multithreading which are Hardware Pipeline, Memory Management Unit (MMU) and Scheduling algorithm, this project a Rate Monotonic Scheduling algorithm was designed for the Amber core. This design can support four threads with a static priority scheduling class for Real Time Operating Systems (RTOSs). This algorithm was also tested for compatiblitity with each stage of the pipeline modified for multithreading. |
| Year | 2015 |
| Corresponding Series Added Entry | Asian Institute of Technology. Caps. Proj. ; no. EL-15-05 |
| Type | Project |
| School | School of Engineering and Technology (SET) |
| Department | Bachelor Degree |
| Academic Program/FoS | Electronic Engineering (EL) |
| Chairperson(s) | Mongkol Ekpanyapong; |
| Examination Committee(s) | Krit Athikulwongse; |
| Degree | Capstone Project (B.Sc.)-Asian Institute of Technology, 2015 |