| Author | Chen, Peng |
| Call Number | AIT Thesis no. CS-95-24 |
| Subject(s) | Multiplication
|
| Note | A thesis submitted in partial fulfilment of the requirement for the degree of Master of Science |
| Publisher | Asian Institute of Technology |
| Abstract | In this thesis, a new design technique, 3n-2m scheme, for array multipliers is presented. Its efficiency and flexibility are analyzed. Comparison with existing designs is discussed. The author also provides its application to some existing array multiplier technique for faster speed. The design to combine multiplication with addition is implemented on the basis of existing multiplier technique and new proposed 3n-2m scheme. |
| Year | 1995 |
| Type | Thesis |
| School | School of Engineering and Technology (SET) |
| Department | Department of Information and Communications Technologies (DICT) |
| Academic Program/FoS | Computer Science (CS) |
| Chairperson(s) | Yulu, Qi; |
| Examination Committee(s) | Murai, Shunji;Huynh, Ngoc Phien |
| Scholarship Donor(s) | SEC; |
| Degree | Thesis (M.Sc.) - Asian Institute of Technology, 1995 |