| Author | Kanlaya Narue-domkul |
| Call Number | AIT Thesis no. CS-94-36 |
| Subject(s) | Parallel processing (Electronic computers)
|
| Note | A thesis submitted in partial fulfillment of the requirement for the degree of Master of Science, School of Engineering and Technology |
| Publisher | Asian Institute of Technology |
| Abstract | This study proposed the systolic algorithms to improve the processing speed with quality
equivalent to the selected facility layout algorithms: Sirinaovakul and Thajchayapong's
algorithm, ALDEP, CORELAP, CRAFT and CLASS. The parallelism is created by
simultaneously computing different exerted energies (or total cost) of all possible alternative
layouts, differenct central points (or centroids) of all possible located patterns, different closeness
weight (or closeness rating) of all possible to-be-located patterns and different distance between
all pairwise combinations separately. The systolic cell of all algorithms has been designed in the
same architecture. The simulation of closeness weight computation has been selected to be
performed on DECPeRLe-1 board using an PerlelDC library. The result has proved that this
proposed approach significantly decreases the processing time when compared to the
uniprocessor facility layout algorithm. On the basis of this simulation, it can be assumed that
other algorithms proposed produce the same result. |
| Year | 1994 |
| Type | Thesis |
| School | School of Engineering and Technology (SET) |
| Department | Other Field of Studies (No Department) |
| Academic Program/FoS | Computer Science (CS) |
| Chairperson(s) | Yulu, Qi
|
| Examination Committee(s) | Murai, Shunji ;Sadananda, Ramakoti
|
| Scholarship Donor(s) | RTG/AIT Cooperation Program for HRD |
| Degree | Thesis (M.Sc.) - Asian Institute of Technology, 1994 |