| Author | Kasem Chaisukpirom |
| Call Number | AIT Thesis no.CS-93-19 |
| Subject(s) | Computer-aided design
|
| Note | A thesis submitted in partial fulfillment of the requirement for the degree of Master of
Engineering |
| Publisher | Asian Institute of Technology |
| Abstract | There have been many proposals for data models to support circuit design. At first glance,
it may appear that many new concepts have been introduced, but indeed there are only a small
number of concepts underlying these proposals. In addition, none of them are described in a
formal way. This study is aimed at the proposal of an object-oriented data model for logic design
and the formal language for describing and creating circuit objects. The language is based on F-Logic.
Some modifications are made to the language to support set operations. Two CAD
prototypes are implemented. The first prototype is built to use the proposed language for logic
design. The graphical user interface is added to the other prototype which makes logic designing
easier. The logic verification is added to the prototypes to check circuit correctness. To simplify
the implementation, the prototypes support only combinational circuits. |
| Year | 1993 |
| Type | Thesis |
| School | School of Engineering and Technology (SET) |
| Department | Department of Information and Communications Technologies (DICT) |
| Academic Program/FoS | Computer Science (CS) |
| Chairperson(s) | Vilas Wuwongse; |
| Examination Committee(s) | Yulu, Qi;Batanov, Dentcho N.; |
| Scholarship Donor(s) | Government of Japan; |
| Degree | Thesis (M.Eng.) - Asian Institute of Technology, 1993 |